18353167. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Hyunsoo Chung of Suwon-si (KR)
Younglyong Kim of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18353167 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application consists of two semiconductor chips stacked on top of each other. The first semiconductor chip has a substrate, multiple pads on the substrate, and through-electrodes that connect the pads. The second semiconductor chip is placed on top of the first chip and has a substrate with pads that are in contact with the pads of the first chip. The pads of the first chip are divided into two groups: the first group has a base layer with a recess, and alternating conductive pattern and insulating pattern layers in the recess, while the second group has a base layer with a recess and a conductive pattern layer in the recess.
- The patent application describes a semiconductor package with stacked chips and specific pad structures.
- The first chip has multiple pads connected by through-electrodes, and the second chip has pads in contact with the first chip's pads.
- The pads of the first chip are divided into two groups, each with a different structure involving recesses and conductive pattern layers.
Potential applications of this technology:
- This semiconductor package design can be used in various electronic devices that require compact and efficient chip stacking.
- It can be applied in mobile devices, such as smartphones and tablets, to save space and improve performance.
- It can also be used in high-performance computing systems, where multiple chips need to be stacked for increased processing power.
Problems solved by this technology:
- The stacked chip design helps overcome space limitations in electronic devices by vertically integrating multiple chips.
- The specific pad structures ensure reliable electrical connections between the stacked chips.
- The recesses and alternating conductive and insulating pattern layers provide a stable and efficient interface between the chips.
Benefits of this technology:
- The semiconductor package allows for increased functionality and performance in electronic devices without significantly increasing their size.
- The stacked chip design enables better thermal management by reducing the distance between chips, improving heat dissipation.
- The specific pad structures ensure reliable signal transmission and reduce the risk of electrical failures in the stacked chips.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads on the first substrate, and a plurality of through-electrodes extending through the first substrate and connected to the plurality of first pads, and a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second substrate, and a plurality of second pads below the second substrate and in contact with the plurality of first pads. The plurality of first pads includes a first group of first pads each including a first base layer including a first recess, and a first conductive pattern layer and a first insulating pattern layer alternately disposed in the first recess, and a second group of first pads each including a second base layer including a second recess, and a second conductive pattern layer disposed in the second recess.
