18341345. SEMICONDUCTOR PACKAGE WITH SUBSTRATE CAVITY simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE WITH SUBSTRATE CAVITY

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Jinduck Park of SUWON-SI (KR)

Chansik Kwon of SUWON-SI (KR)

Yongseong Kim of SUWON-SI (KR)

Inwook Im of SUWON-SI (KR)

Jiyeon Han of SUWON-SI (KR)

SEMICONDUCTOR PACKAGE WITH SUBSTRATE CAVITY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18341345 titled 'SEMICONDUCTOR PACKAGE WITH SUBSTRATE CAVITY

Simplified Explanation

The semiconductor package described in the patent application includes a package base substrate with a substrate cavity formed inside it. The cavity extends from the top surface of the substrate downward towards the bottom surface. The package base substrate also consists of multiple base insulating layers, substrate wiring patterns on the top and bottom surfaces of each layer, and substrate conductive vias passing through the insulating layers and connected to the wiring patterns. Additionally, the package includes multiple semiconductor chips stacked at the bottom of the substrate cavity in a direction perpendicular to the substrate plane.

  • The package base substrate has a substrate cavity that allows for the placement of multiple semiconductor chips.
  • The base insulating layers provide insulation and structural support for the package.
  • The substrate wiring patterns enable electrical connections within the package.
  • The substrate conductive vias allow for the passage of electrical signals between different layers of the package.
  • The stacked arrangement of semiconductor chips maximizes space utilization and enables efficient packaging.

Potential Applications

  • This semiconductor package can be used in various electronic devices such as smartphones, tablets, and computers.
  • It can be employed in automotive electronics, aerospace systems, and industrial equipment that require compact and efficient semiconductor packaging.

Problems Solved

  • The package base substrate with a substrate cavity solves the problem of limited space for accommodating multiple semiconductor chips.
  • The use of base insulating layers and substrate wiring patterns addresses the need for electrical insulation and interconnection within the package.
  • The substrate conductive vias solve the challenge of passing electrical signals between different layers of the package.

Benefits

  • The semiconductor package allows for the integration of multiple chips in a compact form, reducing the overall size of electronic devices.
  • The stacked arrangement of chips enables efficient heat dissipation and improved performance.
  • The use of substrate wiring patterns and conductive vias simplifies the electrical connections and enhances signal integrity within the package.


Original Abstract Submitted

A semiconductor package includes a package base substrate including a substrate cavity formed therein, the substrate cavity extending from a top surface of the package base substrate downwardly toward a bottom surface of the package base substrate. The package base substrate further includes a plurality of base insulating layers, a plurality of substrate wiring patterns extending along at least one of a top surface and a bottom surface of each of the plurality of base insulating layers, and a plurality of substrate conductive vias which pass through at least one of the plurality of base insulating layers and are connected to the plurality of substrate wiring patterns. The semiconductor package further includes a plurality of semiconductor chips disposed at a bottom of the substrate cavity and stacked in a direction perpendicular to a plane of the package base substrate.

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