18335336. PACKAGED INTEGRATED CIRCUIT HAVING ENHANCED ELECTRICAL INTERCONNECTS THEREIN simplified abstract (Samsung Electronics Co., Ltd.)
Contents
PACKAGED INTEGRATED CIRCUIT HAVING ENHANCED ELECTRICAL INTERCONNECTS THEREIN
Organization Name
Inventor(s)
Hyeonjeong Hwang of Suwon-si (KR)
Kyounglim Suk of Suwon-si (KR)
Hyeonseok Lee of Suwon-si (KR)
PACKAGED INTEGRATED CIRCUIT HAVING ENHANCED ELECTRICAL INTERCONNECTS THEREIN - A simplified explanation of the abstract
This abstract first appeared for US patent application 18335336 titled 'PACKAGED INTEGRATED CIRCUIT HAVING ENHANCED ELECTRICAL INTERCONNECTS THEREIN
Simplified Explanation
The patent application describes a packaged integrated circuit with a redistribution layer containing electrically conductive vias and lower pads connected to the vias. The lower pads have a lower under-bump metallization (UBM) layer in contact with external connection terminals and an upper UBM layer contacting the lower UBM layer.
- Lower pads with under-bump metallization (UBM) layers
- Upper UBM layer contacting lower UBM layer
- Greater lateral width dimension on upper surface of lower UBM layer
- External connection terminals electrically connected to lower pads via vias
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- Potential Applications
- Semiconductor packaging
- Integrated circuits
- Electronic devices
- Problems Solved
- Improved electrical connectivity
- Enhanced reliability of connections
- Efficient signal transmission
- Benefits
- Enhanced performance of integrated circuits
- Increased durability of semiconductor chips
- Improved functionality of electronic devices
Original Abstract Submitted
A packaged integrated circuit includes a redistribution layer having a plurality of electrically conductive vias extending at least partially therethrough, and a plurality of lower pads electrically connected to corresponding ones of the plurality of electrically conductive vias. A semiconductor chip is provided on the redistribution layer, and external connection terminals are provided, which electrically contact corresponding ones of the plurality of lower pads within the redistribution layer. Each of the plurality of lower pads includes: (i) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal, and (ii) an upper UBM layer extending on and contacting the lower UBM layer. In addition, an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer, which contacts a corresponding electrically conductive via.
