18334100. METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SACRIFICIAL LAYER AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THEREOF simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SACRIFICIAL LAYER AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THEREOF
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SACRIFICIAL LAYER AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THEREOF - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SACRIFICIAL LAYER AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THEREOF
Organization Name
Inventor(s)
Young Lyong Kim of Suwon-si (KR)
Hyun Soo Chung of Suwon-si (KR)
METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SACRIFICIAL LAYER AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18334100 titled 'METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SACRIFICIAL LAYER AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THEREOF
Simplified Explanation
The method described in the patent application involves manufacturing a semiconductor package by mounting semiconductor chips on an interposer, forming a molding part between the chips, surrounding bumps with underfill, forming sacrificial and wafer level molding layers, planarizing the layers, removing sacrificial pattern, sawing the package, mounting the interposer on a package board, surrounding bumps with underfill, and attaching a stiffener to the package board.
- Mounting semiconductor chips on an interposer
- Forming molding part between semiconductor chips
- Surrounding bumps with underfill
- Forming sacrificial layer covering semiconductor chips
- Forming wafer level molding layer covering sacrificial layer
- Planarizing to expose upper sides of semiconductor chips
- Forming sacrificial pattern and wafer level molding pattern
- Removing sacrificial pattern
- Sawing to remove outer edge of semiconductor package
- Mounting interposer on package board
- Surrounding bumps with underfill
- Attaching stiffener to outer portion of package board
Potential Applications
The technology described in this patent application can be applied in the manufacturing of various semiconductor packages used in electronic devices such as smartphones, tablets, computers, and other consumer electronics.
Problems Solved
This technology solves the problem of efficiently and effectively manufacturing semiconductor packages with improved structural integrity and reliability.
Benefits
The benefits of this technology include enhanced durability, increased performance, and reduced manufacturing costs for semiconductor packages.
Potential Commercial Applications
The potential commercial applications of this technology include semiconductor packaging companies, electronics manufacturers, and suppliers in the semiconductor industry.
Possible Prior Art
One possible prior art related to this technology is the use of underfill materials in semiconductor packaging processes to enhance the mechanical strength and reliability of the package.
Unanswered Questions
How does this technology compare to existing methods of semiconductor packaging?
This article does not provide a direct comparison between this technology and existing methods of semiconductor packaging.
What are the specific materials used in the underfill and molding layers in this process?
The article does not specify the exact materials used in the underfill and molding layers in this process.
Original Abstract Submitted
A method for manufacturing a semiconductor package includes mounting semiconductor chips on an interposer, forming a molding part between the semiconductor chips, surrounding a plurality of bumps between the semiconductor chips and the interposer with a first underfill, forming a sacrificial layer that covers the semiconductor chips, forming a wafer level molding layer that covers the sacrificial layer, performing a planarization process to expose upper sides of the semiconductor chips, form the sacrificial layer into a sacrificial pattern, and form the wafer level molding layer into a wafer level molding pattern, removing the sacrificial pattern, performing a sawing process to remove an outer edge of the semiconductor package, mounting the interposer on a side of a package board, surrounding a plurality of bumps between the package board and the interposer with a second underfill, and attaching a stiffener to an outer portion of the package board.
