18330731. DUAL-EDGE-TRIGGERED FLIP-FLOP simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
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DUAL-EDGE-TRIGGERED FLIP-FLOP
Organization Name
Inventor(s)
DUAL-EDGE-TRIGGERED FLIP-FLOP - A simplified explanation of the abstract
This abstract first appeared for US patent application 18330731 titled 'DUAL-EDGE-TRIGGERED FLIP-FLOP
Simplified Explanation
The abstract of the patent application describes a flip-flop circuit that consists of an input logic circuit, a first latch, a second latch, and an output multiplexer. The input logic circuit generates a clock bar signal based on an input data bit and a clock signal. The first and second latches operate based on the input data bit, the clock signal, and the clock bar signal. The output multiplexer operates based on the outputs from the first and second latches and outputs an output data bit. The input logic circuit maintains a constant value when there is no change in the output data bit.
- The flip-flop circuit includes an input logic circuit that generates a clock bar signal based on input data and a clock signal.
- The first and second latches operate based on the input data, clock signal, and clock bar signal.
- An output multiplexer combines outputs from the first and second latches to produce an output data bit.
- The input logic circuit maintains a constant value when the output data bit remains unchanged.
Potential applications of this technology:
- Digital circuits and systems
- Computer processors and microcontrollers
- Communication systems and networks
Problems solved by this technology:
- Ensures stable and reliable data storage and transfer in digital systems
- Reduces the risk of data corruption and errors
- Improves the overall performance and efficiency of digital circuits
Benefits of this technology:
- Increased reliability and stability in data storage and transfer
- Enhanced performance and efficiency of digital systems
- Reduced risk of data corruption and errors
Original Abstract Submitted
A flip-flop includes an input logic circuit, a first latch, a second latch, and an output multiplexer; where the input logic circuit outputs a clock bar signal based on an input data bit and a clock signal, where the first latch and the second latch operate based on the input data bit, the clock signal, and a clock bar signal, where the output multiplexer operates based on outputs from nodes of the first and second nodes and outputs an output data bit, and where the input logic circuit has a uniform value in a period where there is no change of a value of the output data bit.
