18329530. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18329530 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package that consists of two wiring structures, a semiconductor chip, an encapsulant, and connection structures.
- The first wiring structure includes multiple redistribution patterns with bottom and top connection pads, surrounded by insulation layers.
- The second wiring structure also includes multiple redistribution patterns with bottom and top connection pads, surrounded by insulation layers.
- The semiconductor chip is placed between the first and second wiring structures.
- The encapsulant fills the space between the two wiring structures.
- The connection structures pass through the encapsulant and connect the top connection pads of the first structure to the bottom connection pads of the second structure, arranged around the semiconductor chip.
Potential applications of this technology:
- Semiconductor packaging for integrated circuits and electronic devices.
- Improving the electrical connections and signal transmission within a semiconductor package.
Problems solved by this technology:
- Provides a reliable and efficient method for connecting the top and bottom connection pads of different wiring structures.
- Enhances the overall performance and functionality of the semiconductor package.
Benefits of this technology:
- Improved electrical connectivity and signal transmission.
- Enhanced reliability and durability of the semiconductor package.
- Efficient use of space within the package.
- Facilitates the integration of multiple wiring structures and redistribution patterns.
Original Abstract Submitted
A semiconductor package includes a first wiring structure including a plurality of first redistribution patterns having a plurality of first bottom connection pads and a plurality of first top connection pads and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns, a second wiring structure including a plurality of second redistribution patterns having a plurality of second bottom connection pads and a plurality of second top connection pads and a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a semiconductor chip interposed between the first wiring structure and the second wiring structure, an encapsulant filling a space between the first wiring structure and the second wiring structure, and a plurality of connection structures passing through the encapsulant and connecting the plurality of first top connection pads to the plurality of second bottom connection pads and arranged around the semiconductor chip.
