18326554. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
HYUNGCHUL Shin of Suwon-si (KR)
GWANGJAE Jeon of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18326554 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes two semiconductor chips stacked on top of each other, with the second chip placed on the first chip.
- The first semiconductor chip has main and edge regions, with main and dummy pads on the top surface.
- The second semiconductor chip has a semiconductor substrate, wiring layer with dielectric layer and patterns, and main and dummy pads below the wiring layer.
- The wiring layer is thicker on the main region of the second chip compared to the edge region.
- Potential Applications
- Advanced semiconductor packaging technology for compact electronic devices.
- Improved performance and reliability of stacked semiconductor chips.
- Problems Solved
- Efficient stacking of semiconductor chips without compromising on performance.
- Enhanced thermal management and electrical connectivity in semiconductor packages.
- Benefits
- Higher integration density in electronic devices.
- Enhanced signal transmission and reduced signal interference.
- Improved thermal dissipation for better overall performance.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first main region and a first edge region, and a second semiconductor chip on the first semiconductor chip and including a second main region and a second edge region. The first semiconductor chip includes a first main pad and a first dummy pad respectively on the first main region and the first edge region on a top surface of the first semiconductor chip. The second semiconductor chip includes a first semiconductor substrate, a wiring layer below the first semiconductor substrate and including a wiring dielectric layer and wiring patterns, a second main pad and a second dummy pad respectively on the second main region and the second edge region below the wiring layer. A thickness of the wiring layer is greater on the second main region than on the second edge region.
