18325307. MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME
Organization Name
Inventor(s)
Kangsub Jeong of Suwon-si (KR)
MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18325307 titled 'MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME
Simplified Explanation
The memory core circuit described in the patent application consists of a memory cell array with sub cell arrays and a core control circuit with sub peripheral circuits. Each sub peripheral circuit is positioned underneath a corresponding sub cell array and includes various components such as wordline drivers, bitline sense amplifiers, row decoding circuit, power circuit, and control circuit.
- Memory core circuit with CoP structure
- Sub cell arrays with memory cells connected to wordlines and bitlines
- Sub peripheral circuits with wordline drivers, sense amplifiers, row decoding circuit, power circuit, and control circuit
- Efficient design reducing size and enhancing design margin
Potential Applications
The technology described in this patent application could be applied in various memory devices such as RAM, ROM, and flash memory.
Problems Solved
1. Efficient utilization of space in memory core circuits 2. Enhanced design margin for improved performance
Benefits
1. Reduced size of memory core circuits 2. Enhanced design margin for better reliability 3. Improved efficiency in memory operations
Potential Commercial Applications
Optimizing memory core circuits for consumer electronics, data storage devices, and computing systems.
Possible Prior Art
Prior art may include similar memory core circuit designs with sub peripheral circuits, but the specific CoP structure described in this patent application may be a novel innovation.
Unanswered Questions
How does the CoP structure specifically contribute to reducing the size of the memory core circuit?
The abstract mentions that the CoP structure efficiently provides the core control circuit, but the exact mechanism or design details are not elaborated on.
What specific improvements in design margin can be achieved with this technology?
While the abstract mentions that the design margin may be enhanced, it does not specify the extent of improvement or the specific factors that contribute to this enhancement.
Original Abstract Submitted
A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.
