18319135. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Kyounglim Suk of Suwon-si (KR)
Hyeonjeong Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18319135 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a redistribution structure with stacked redistribution and insulating layers, a semiconductor chip connected to the redistribution layer, and bumps on the structure. The redistribution structure features vias and under bump metallurgy (UBM) structures for electrical connections between the vias and bumps.
- The semiconductor package includes a redistribution structure with stacked redistribution and insulating layers.
- A semiconductor chip is electrically connected to the redistribution layer within the package.
- Bumps are present on the redistribution structure for various purposes.
- Vias extend from the redistribution layer in a vertical stacking direction of the structure.
- Under bump metallurgy (UBM) structures are electrically connected between the vias and bumps, facing the bumps in the vertical stacking direction.
- Each UBM structure consists of a first UBM layer with a metal material or alloy, and a second UBM layer with a different metal material.
Potential Applications
This technology can be applied in the manufacturing of advanced semiconductor packages for various electronic devices, such as smartphones, tablets, and computers.
Problems Solved
This technology solves the problem of efficient electrical connections between semiconductor chips and external components in a compact and reliable manner.
Benefits
The benefits of this technology include improved performance, increased reliability, and enhanced functionality of semiconductor packages in electronic devices.
Potential Commercial Applications
The potential commercial applications of this technology include the semiconductor industry, electronics manufacturing companies, and consumer electronics companies.
Possible Prior Art
One possible prior art in this field is the use of UBM structures in semiconductor packaging to improve electrical connections and reliability.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods in terms of cost and efficiency?
This article does not provide a direct comparison with existing semiconductor packaging methods in terms of cost and efficiency. It would be beneficial to understand how this technology stacks up against current practices in the industry.
What are the environmental implications of using this technology in semiconductor manufacturing processes?
The environmental impact of using this technology in semiconductor manufacturing processes is not addressed in the article. It would be important to consider the sustainability aspects of implementing this innovation in the industry.
Original Abstract Submitted
A semiconductor package includes a redistribution structure in which at least one redistribution layer and at least one insulating layer are alternately stacked; a semiconductor chip electrically connected to the at least one redistribution layer; and bumps on the redistribution structure, wherein the redistribution structure includes vias extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (UBM) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the UBM structures includes a first UBM layer including a first metal material or an alloy of the first metal material; and a second UBM layer between one of the bumps and the first UBM layer and including a second metal material.
