18319049. POWER LINE ARRANGEMENT METHOD ANDMEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
POWER LINE ARRANGEMENT METHOD ANDMEMORY DEVICE
Organization Name
Inventor(s)
Jonghyeok Kim of Suwon-si (KR)
POWER LINE ARRANGEMENT METHOD ANDMEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18319049 titled 'POWER LINE ARRANGEMENT METHOD ANDMEMORY DEVICE
Simplified Explanation
The abstract describes a method for arranging power lines in a memory device with multiple layers. The power lines and signal lines are arranged along track lines in each layer, which can be separated from each other in different directions. The method involves identifying a track line with multiple power lines, moving at least one of the power lines to an adjacent track line, and electrically connecting the moved power line on the second track line.
- The method is used for arranging power lines and signal lines in a memory device with multiple layers.
- Power lines and signal lines are arranged along track lines in each layer.
- The track lines can be separated from each other in different directions.
- The method involves identifying a track line with multiple power lines.
- At least one power line is moved to an adjacent track line.
- The moved power line is electrically connected on the second track line.
Potential Applications:
- Memory devices with multiple layers, such as DRAM or NAND flash memory.
- Integrated circuits and semiconductor devices that require efficient power line arrangements.
Problems Solved:
- Efficient arrangement of power lines and signal lines in memory devices with multiple layers.
- Minimizing interference between power lines and signal lines.
- Optimizing the use of available space in the memory device.
Benefits:
- Improved performance and reliability of memory devices.
- Enhanced power distribution and signal integrity.
- Increased density of power lines and signal lines in memory devices.
- Cost-effective manufacturing process for memory devices.
Original Abstract Submitted
A method of arranging power lines to be applied to a memory device including a plurality of layers, wherein, in each of the plurality of layers, a plurality of power lines and a plurality of signal lines are arranged along a plurality of track lines arranged side by side to be separated from each other in a first direction or a second direction that is perpendicular to the first direction is provided. The method includes identifying a first track line on which a plurality of power lines are arranged, moving at least one of the plurality of power lines to a second track line adjacent to the first track line, and electrically connecting the moved at least one power line on the second track line.
