18315689. HIGHLY INTEGRATED SEMICONDUCTOR DEVICE CONTAINING MULTIPLE BONDED DIES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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HIGHLY INTEGRATED SEMICONDUCTOR DEVICE CONTAINING MULTIPLE BONDED DIES

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Ae-Nee Jang of Suwon-si (KR)

Jihoon Kim of Suwon-si (KR)

Seungduk Baek of Suwon-si (KR)

Hyuekjae Lee of Suwon-si (KR)

HIGHLY INTEGRATED SEMICONDUCTOR DEVICE CONTAINING MULTIPLE BONDED DIES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18315689 titled 'HIGHLY INTEGRATED SEMICONDUCTOR DEVICE CONTAINING MULTIPLE BONDED DIES

Simplified Explanation

The semiconductor device described in the abstract includes a lower die with a first semiconductor substrate, a first semiconductor element, a first pad, and a first interconnection structure. An upper die is bonded to the lower die, with the first pad of the lower die in contact with a second pad of the upper die.

  • Lower die with first semiconductor substrate, first semiconductor element, first pad, and first interconnection structure
  • Upper die bonded to lower die with first pad in contact with second pad

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      1. Potential Applications
  • Semiconductor manufacturing
  • Integrated circuits
  • Electronics industry
      1. Problems Solved
  • Improved interconnection structure
  • Enhanced bonding between dies
  • Increased efficiency in semiconductor devices
      1. Benefits
  • Better performance in semiconductor devices
  • Enhanced reliability
  • Improved overall functionality


Original Abstract Submitted

A semiconductor device includes a substrate and a lower die on the substrate. The lower die includes a first semiconductor substrate having a first device region and a first edge region therein, a first semiconductor element on the first device region, a first pad on the first device region and on the first semiconductor element, and a first interconnection structure connecting the first semiconductor element to the first pad. The first interconnection structure includes a first signal pattern on the first device region and connected to the first semiconductor element, a second signal pattern on the first device region and directly connected to the first pad, and a first dummy pattern at the same level as the second signal pattern and disposed on the first edge region. An upper die is provided, which is bonded to the lower die such that the first pad of the lower die is in contact with a second pad of the upper die.