18314536. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Hui-Zhong Zhuang of Hsinchu (TW)
Johnny Chiahoa Li of Hsinchu (TW)
Jung-Chan Yang of Hsinchu (TW)
Jerry Chang Jui Kao of Hsinchu (TW)
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18314536 titled 'INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
Simplified Explanation
The abstract describes a flip-flop design that includes four active regions on a substrate, each corresponding to a set of transistors of different types. The flip-flop also includes a gate structure on a different level, overlapping two of the active regions, and is configured to receive a clock signal.
- The flip-flop design includes four active regions on a substrate.
- Each active region corresponds to a set of transistors of different types.
- The flip-flop includes a gate structure on a different level.
- The gate structure overlaps at least two of the active regions.
- The gate structure is configured to receive a clock signal.
Potential Applications:
- Integrated circuits and semiconductor devices
- Digital logic circuits
- Memory elements and storage devices
Problems Solved by this Technology:
- Efficient and reliable storage and retrieval of digital information
- Reduction of power consumption in digital circuits
- Improved performance and speed of digital logic circuits
Benefits of this Technology:
- Compact and space-efficient design
- Compatibility with different types of transistors
- Improved reliability and stability of flip-flop operation
- Reduction in power consumption and heat generation
Original Abstract Submitted
A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.
