18311289. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18311289 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package design that improves the reliability of stacked semiconductor packages. The package includes two semiconductor chips, with the first chip having through silicon vias (TSVs) and upper conductive pads connected to the TSVs. The second chip is placed on top of the first chip and has lower conductive pads on its lower surface. Conductive bumps are used to connect the upper conductive pads to the lower conductive pads. An interlayer adhesive layer is present between the two chips, and there is an interlayer space between them that overlaps in a vertical direction. The encapsulant material extends into this interlayer space.
- The patent describes a semiconductor package design that enhances the reliability of stacked semiconductor packages.
- The design includes through silicon vias (TSVs) and conductive pads to improve electrical connections between the semiconductor chips.
- The use of conductive bumps ensures proper electrical connections between the upper and lower conductive pads.
- The interlayer adhesive layer provides structural support and stability between the two semiconductor chips.
- The interlayer space allows for the encapsulant material to extend into it, providing additional protection and stability to the package.
Potential Applications:
- This technology can be applied in various electronic devices that utilize stacked semiconductor packages, such as smartphones, tablets, and laptops.
- It can also be used in high-performance computing systems, data centers, and automotive electronics.
Problems Solved:
- The design addresses the reliability issues associated with stacked semiconductor packages by improving the electrical connections between the chips.
- It solves the problem of potential delamination or detachment between the semiconductor chips by using an interlayer adhesive layer.
- The interlayer space and encapsulant material provide additional protection against external factors like moisture, dust, and mechanical stress.
Benefits:
- Improved reliability and performance of stacked semiconductor packages.
- Enhanced electrical connections between semiconductor chips, leading to better signal transmission and reduced signal loss.
- Increased structural stability and resistance to delamination or detachment.
- Enhanced protection against environmental factors, ensuring longevity and durability of the semiconductor package.
Original Abstract Submitted
The reliability of stacked semiconductor packages may be improved via a semiconductor package including a first semiconductor chip including through silicon vias (TSVs) with respective upper conductive pads electrically connected to the TSVs, a second semiconductor chip on the first semiconductor chip with lower conductive pads on a lower surface of the second semiconductor chip, conductive bumps between the upper conductive pads and the lower conductive pads, and an interlayer adhesive layer between the first semiconductor chip and the second semiconductor chip. An interlayer space is between the first semiconductor chip and the second semiconductor chip and overlaps the first semiconductor chip and the second semiconductor chip in a vertical direction. The encapsulant extends into the interlayer space.
