18308358. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)

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SEMICONDUCTOR PACKAGE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Joonghyun Baek of Suwon-si (KR)

In Lee of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18308358 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in the abstract includes:

  • A substrate with a wiring circuit
  • An interposer with an interconnect circuit, having a first side, second side, third side, and fourth side
  • First and second buffer chips on the interposer
  • First and second chip stacks adjacent to the first and second sides of the interposer, respectively
  • A third chip stack adjacent to the third side of the interposer, with two groups of semiconductor chips connected to the buffer chips via the interconnect circuit
    • Potential Applications:**

- High-performance computing - Data centers - Artificial intelligence/machine learning applications

    • Problems Solved:**

- Improved electrical connectivity between chips - Enhanced performance and reliability of semiconductor packages - Efficient heat dissipation

    • Benefits:**

- Higher processing speeds - Increased data transfer rates - Enhanced overall system performance


Original Abstract Submitted

A semiconductor package includes: a substrate that includes a wiring circuit; an interposer on the substrate, wherein the interposer includes a first side and a second side opposing each other and a third side and a fourth side between the first side and the second side, and wherein the interposer includes an interconnect circuit electrically connected to the wiring circuit; a first and second buffer chips on the interposer; a first chip stack adjacent to the first side of the interposer and connected to the first buffer chip; a second chip stack adjacent to the second side of the interposer and connected to the second buffer chip; a third chip stack adjacent to the third side of the interposer, and wherein the third chip stack includes first and second groups of semiconductor chips, which are electrically connected to the first and second buffer chips, respectively, via the interconnect circuit.