18307259. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Kyoungwoo Lee of Suwon-si (KR)
Anthony Dongick Lee of Suwon-si (KR)
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18307259 titled 'SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
Simplified Explanation
The semiconductor device described in the patent application includes a substrate with active patterns, source/drain patterns, active contacts, upper contacts, lower power interconnection line, buried interconnection portion, lower contact portion, and barrier pattern.
- The device has active patterns and source/drain patterns on the substrate.
- Active contacts are present on the source/drain patterns.
- An upper contact extends from the active contact towards the substrate, between the active patterns.
- A lower power interconnection line is buried in the substrate, with a buried interconnection portion and a lower contact portion extending to the bottom surface of the upper contact.
- A barrier pattern is provided between the lower contact portion and the upper contact.
Potential applications of this technology:
- Semiconductor manufacturing
- Integrated circuits
- Electronic devices
Problems solved by this technology:
- Efficient power distribution within semiconductor devices
- Improved interconnection design
- Enhanced performance and reliability of electronic components
Benefits of this technology:
- Increased efficiency in power distribution
- Enhanced performance of semiconductor devices
- Improved reliability and longevity of electronic products
Original Abstract Submitted
A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.
