18306004. VERTICALLY STACKED TRANSISTORS AND FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

VERTICALLY STACKED TRANSISTORS AND FABRICATION THEREOF

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chien-Te Tu of Hsinchu City (TW)

Chee-Wee Liu of Taipei City (TW)

VERTICALLY STACKED TRANSISTORS AND FABRICATION THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18306004 titled 'VERTICALLY STACKED TRANSISTORS AND FABRICATION THEREOF

Simplified Explanation

The device described in the patent application consists of a structure with multiple semiconductor layers and a gate structure.

• The device includes a first semiconductor layer on top of a substrate, with a first channel region and source/drain regions on either side.
• A dielectric layer is placed over the first semiconductor layer.
• A second semiconductor layer is then placed over the dielectric layer, with a second channel region and source/drain regions.
• The gate structure consists of three portions: one extending in the dielectric layer, one wrapping around the first channel region, and one wrapping around the second channel region.

• • Potential Applications:**

• Advanced semiconductor devices
• High-performance transistors
• Integrated circuits

• • Problems Solved:**

• Enhancing performance of semiconductor devices
• Improving efficiency of transistors
• Increasing integration density of circuits

• • Benefits:**

• Improved speed and efficiency of electronic devices
• Higher integration density for smaller and more powerful devices
• Enhanced overall performance of semiconductor technology

Original Abstract Submitted

A device comprises a first semiconductor layer, a dielectric layer, a second semiconductor layer, and a gate structure. The first semiconductor layer is over a substrate. The first semiconductor layer comprises a first channel region and first source/drain regions on opposite sides of the first channel region. The dielectric layer is over the first semiconductor layer. The second semiconductor layer is over the dielectric layer. The second semiconductor layer comprises a second channel region and second source/drain regions on opposite sides of the second channel region. The gate structure comprises a first portion extending in the dielectric layer, a second portion wrapping around the first channel region of the first semiconductor layer, and a third portion wrapping around the second channel region of the second semiconductor layer.