18303641. CHIP PACKAGE AND METHODS FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company Limited)

CHIP PACKAGE AND METHODS FOR FORMING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company Limited

Inventor(s)

Kuan-Yu Huang of Taipei (TW)

Sung-Hui Huang of DongshanTownship (TW)

Kuo-Chiang Ting of Hsinchu City (TW)

Chia-Hao Hsu of Hsinchu (TW)

Hsien-Pin Hsu of Zhubei City (TW)

Chih-Ta Shen of Hsinchu (TW)

Shang-Yun Hou of Jubei City (TW)

CHIP PACKAGE AND METHODS FOR FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18303641 titled 'CHIP PACKAGE AND METHODS FOR FORMING THE SAME

Simplified Explanation

The bonded assembly described in the patent application includes an interposer, a semiconductor die with a contoured sidewall, a high bandwidth memory (HBM) die, and a dielectric material portion connecting the semiconductor die and the interposer.

• The semiconductor die has a planar horizontal bottom surface and a contoured sidewall with a vertical segment and a non-horizontal, non-vertical surface segment.
• The contoured sidewall reduces local stress in the HBM die by providing variable lateral spacing from the HBM die.

Potential Applications

The technology described in the patent application could be applied in the manufacturing of high-performance computing devices, such as graphics cards, servers, and artificial intelligence systems.

Problems Solved

This technology helps reduce local stress in the HBM die, which can improve the overall reliability and performance of the bonded assembly.

Benefits

The contoured sidewall design provides a more efficient and reliable connection between the semiconductor die, the HBM die, and the interposer, leading to enhanced overall performance and longevity of the bonded assembly.

Potential Commercial Applications

The technology could be utilized in the production of advanced electronic devices for various industries, including data centers, telecommunications, and automotive.

Possible Prior Art

One possible prior art could be the use of traditional bonding techniques in semiconductor packaging, which may not offer the same level of stress reduction and performance optimization as the contoured sidewall design described in the patent application.

Unanswered Questions

How does the contoured sidewall design impact the thermal performance of the bonded assembly?

The article does not provide information on how the contoured sidewall design affects the thermal characteristics of the bonded assembly.

What are the potential cost implications of implementing this technology in semiconductor manufacturing processes?

The article does not address the potential cost considerations associated with integrating the contoured sidewall design into semiconductor manufacturing processes.

Original Abstract Submitted

A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.