18301403. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Unbyoung Kang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18301403 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The semiconductor package described in the abstract includes a first redistribution structure, a first semiconductor chip with a first through-electrode, a second semiconductor chip stacked on the first chip, a molding layer, a second redistribution structure, and vertical connection wires.
- The package consists of multiple semiconductor chips stacked on top of each other.
- The first semiconductor chip has a through-electrode that extends through the chip.
- The second semiconductor chip is positioned above the first chip, with a central portion overlapping the first chip vertically and an outer portion offset horizontally.
- A molding layer is in contact with the first redistribution structure, the first semiconductor chip, and the second semiconductor chip.
- The second redistribution structure is located on the second semiconductor chip and the molding layer.
- Vertical connection wires extend through the molding layer, connecting the first and second redistribution structures.
Potential Applications
This technology could be applied in:
- Advanced electronic devices
- High-density integrated circuits
- Semiconductor packaging industry
Problems Solved
This technology helps in:
- Increasing the efficiency of semiconductor packages
- Enhancing the performance of stacked semiconductor chips
- Improving the reliability of vertical connections in semiconductor packaging
Benefits
The benefits of this technology include:
- Higher integration levels
- Improved signal transmission
- Enhanced overall performance of electronic devices
Potential Commercial Applications
This technology could be commercially benefit:
- Semiconductor manufacturing companies
- Electronics industry suppliers
- Research and development firms
Possible Prior Art
One possible prior art for this technology could be the use of vertical connection wires in semiconductor packaging to improve signal transmission and integration levels.
Unanswered Questions
How does this technology compare to traditional semiconductor packaging methods?
This article does not provide a direct comparison between this innovative semiconductor package and traditional packaging methods. It would be interesting to know the specific advantages and disadvantages of this new approach compared to existing techniques.
What are the potential challenges in implementing this technology on a large scale?
The article does not address the potential challenges that may arise when implementing this technology on a mass production scale. Understanding the obstacles and limitations of this innovation could provide valuable insights for future development and commercialization efforts.
Original Abstract Submitted
A semiconductor package includes a first redistribution structure, a first semiconductor chip on the first redistribution structure and including a first through-electrode, a second semiconductor chip on the first semiconductor chip and including a central portion vertically overlapping the first semiconductor chip and an outer portion horizontally offset from a sidewall of the first semiconductor chip, a molding layer in contact with the first redistribution structure, the first semiconductor chip, and the second semiconductor chip, a second redistribution structure on the second semiconductor chip and the molding layer, a first vertical connection wire extending through the molding layer and extending from the first redistribution structure to the second redistribution structure, and a second vertical connection wire extending through the molding layer and extending from the first redistribution structure to the outer portion of the second semiconductor chip.
