18300022. VERTICAL TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
VERTICAL TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
Organization Name
Inventor(s)
VERTICAL TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18300022 titled 'VERTICAL TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
Simplified Explanation
- Vertical nonvolatile memory devices and related methods may reduce chip size.
- The nonvolatile memory device includes a substrate with a cell array area and an extension area.
- The device includes multiple gate layers and metal contacts for electrical coupling.
- Channel structures extend through the gate layers in the cell array area.
- Electrode pads provide electrical coupling with the gate layers.
Potential Applications
This technology can be used in various electronic devices such as smartphones, tablets, and laptops to increase memory capacity and reduce chip size.
Problems Solved
This technology solves the problem of limited memory capacity in electronic devices and helps in reducing the overall size of the memory chip.
Benefits
- Increased memory capacity - Reduced chip size - Improved performance in electronic devices
Original Abstract Submitted
According to some embodiments of inventive concepts, vertical nonvolatile memory devices and related methods may reduce chip size. The nonvolatile memory device may include a substrate wherein a first direction is orthogonal with respect to a surface of the substrate and wherein the substrate includes a cell array area and an extension area. A first gate structure layer on the substrate may include a plurality of first gate layers. A contact separation layer may be on the first gate structure layer on the extension area. A second gate structure layer on the first gate structure layer and on the contact separation layer may include a plurality of second gate layers. A plurality of channel structures may extend in the first direction through the first and second gate structure layers on the cell array area. A plurality of first metal contacts may extend through the first gate structure layer in the first direction between the substate and the contact separation layer in the extension area. A plurality of second metal contacts may extend through the second gate structure layer in the first direction in the extension area. The contact separation layer may be between the first plurality of metal contacts and the second plurality of metal contacts, and each of the second metal contacts may be aligned with a respective one of the first metal contacts in the first direction. The device may also include a plurality of first electrode pads and a plurality of second electrode pads. Each of the first electrode pads may extend from a sidewall of a respective one of the first metal contacts to provide electrical coupling with a respective one of the first gate layers. Each of the second electrode pads may extend from a sidewall of a respective one of the second metal contacts to provide electrical coupling with a respective one of the second gate layers.
