18299795. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Unbyoung Kang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18299795 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes multiple layers of redistribution wiring, semiconductor devices, sealing members, and bonding wirings for electrical connections.
- The package has a first redistribution wiring layer with a semiconductor device on top, followed by a sealing member and a second redistribution wiring layer with at least one more semiconductor device on top.
- Bonding wirings are used to connect the redistribution connection pads on the different layers of wiring.
Potential Applications
- Semiconductor packaging for electronic devices
- Integrated circuits in consumer electronics
- Automotive electronics
Problems Solved
- Efficient electrical connections between semiconductor devices
- Improved packaging for compact electronic devices
- Enhanced reliability and performance of semiconductor components
Benefits
- Higher integration density
- Improved electrical connectivity
- Enhanced reliability and durability of semiconductor packages
Original Abstract Submitted
A semiconductor package includes a first redistribution wiring layer, a first semiconductor device on an upper surface of the first redistribution wiring layer, a first sealing member on the first semiconductor device, a second redistribution wiring layer on the first sealing member such that a peripheral region of a lower surface of the second redistribution wiring layer is free of the first sealing member, at least one second semiconductor device on an upper surface of the second redistribution wiring layer, and a plurality of bonding wirings electrically connecting first redistribution connection pads on a lower surface of the first redistribution wiring layer and second redistribution connection pads on the peripheral region of the lower surface of the second redistribution wiring layer.
