18298629. SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED CONDUCTIVE FEATURES simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED CONDUCTIVE FEATURES

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chung-Hao Cai of Hsinchu (TW)

Chao-Hsun Wang of Taoyuan County (TW)

Chia-Hsien Yao of Hsinchu City (TW)

Wang-Jung Hsueh of New Taipei City (TW)

Yen-Jun Huang of Hsinchu (TW)

Fu-Kai Yang of Hsinchu City (TW)

Mei-Yun Wang of Hsinchu (TW)

SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED CONDUCTIVE FEATURES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18298629 titled 'SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED CONDUCTIVE FEATURES

Simplified Explanation

The abstract describes a method of forming a semiconductor structure. Here are the bullet points explaining the patent/innovation:

• A semiconductor substrate is provided with a source/drain feature and a gate structure formed on it.
• An interlayer dielectric layer is formed on the semiconductor substrate.
• The interlayer dielectric layer is patterned to create a trench that exposes the source/drain feature.
• A dielectric liner is formed on the sidewalls of the trench.
• The trench is filled with a metal layer.
• A portion of the metal layer in the trench is recessed, creating a recess in the metal layer.
• A dielectric material layer is refilled in the recess.

Potential applications of this technology:

• This method can be used in the fabrication of semiconductor devices, such as transistors, integrated circuits, and microprocessors.
• It can improve the performance and reliability of semiconductor devices by enhancing the electrical properties and reducing parasitic capacitance.

Problems solved by this technology:

• The method allows for the formation of a recessed metal layer, which can reduce the resistance and improve the contact between the metal layer and the source/drain feature.
• It also helps to prevent the formation of voids or gaps in the metal layer, which can negatively impact device performance.

Benefits of this technology:

• Improved electrical properties and reduced parasitic capacitance can lead to faster and more efficient semiconductor devices.
• The recessed metal layer enhances the contact between the metal and the source/drain feature, improving device performance.
• The method provides a reliable and scalable process for forming semiconductor structures with recessed metal layers.

Original Abstract Submitted

A method of forming a semiconductor structure includes providing a semiconductor substrate having a source/drain feature and a gate structure formed thereon; forming an interlayer dielectric layer on the semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the trench; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling a dielectric material layer in the recess.