18298277. Isolation Structures in Semiconductor Devices simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
Isolation Structures in Semiconductor Devices
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Cheng-Wei Chang of Taipei City (TW)
Shahaji B. More of Hsinchu City (TW)
Lun-Kuang Tan of Hsinchu City (TW)
Chi-Yu Chou of Hsinchu County (TW)
Yueh-Ching Pai of Taichung City (TW)
Isolation Structures in Semiconductor Devices - A simplified explanation of the abstract
This abstract first appeared for US patent application 18298277 titled 'Isolation Structures in Semiconductor Devices
Simplified Explanation
The method of fabricating a semiconductor device involves creating a dummy structure with channel layers, inner spacers, and a gate structure.
- First trench is formed perpendicular to the gate structure, dividing it into segments.
- First isolation feature is deposited in the first trench.
- Gate structure and channel layers are etched to form a second trench exposing inner spacers.
- Second isolation feature is deposited in the second trench, intersecting the first isolation feature.
Potential Applications
- Semiconductor manufacturing industry
- Electronics industry
Problems Solved
- Improved isolation of components in semiconductor devices
- Enhanced performance and reliability of semiconductor devices
Benefits
- Increased efficiency in fabrication process
- Enhanced functionality of semiconductor devices
- Improved overall performance and reliability
Original Abstract Submitted
A method of fabricating a semiconductor device includes providing a dummy structure that includes channel layers, inner spacers disposed between adjacent ones of the channel layers, and a gate structure extending lengthwise in a first direction. A first trench extending lengthwise perpendicular to the first direction is formed, which divides the gate structure into segments. A first isolation feature is deposited in the first trench. The method also includes etching the gate structure and the channel layers to form a second trench extending lengthwise in the first direction. The second trench exposes the inner spacers. A second isolation feature is deposited in the second trench. The second isolation feature intersects the first isolation feature in a top view of the semiconductor device.
