18296640. MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT
Organization Name
Inventor(s)
Seunghyun Cho of Suwon-si (KR)
MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18296640 titled 'MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT
Simplified Explanation
The abstract describes a memory device that includes a memory cell array with multiple rows and columns. The columns are grouped into ticks, which include normal ticks and a spare tick that covers redundancy columns. The device also includes a repair circuit that can repair failed columns by replacing their source address with a destination address of a pass column in a normal tick. The repair circuit can further repair the destination address by replacing it with a redundancy column within the spare tick corresponding to the destination address.
- The memory device has a memory cell array with rows and columns grouped into ticks.
- The ticks include normal ticks and a spare tick for redundancy columns.
- A repair circuit is provided to repair failed columns.
- The repair circuit replaces the source address of a failed column with the destination address of a pass column in a normal tick.
- The repair circuit can further repair the destination address by replacing it with a redundancy column within the spare tick.
Potential applications of this technology:
- Memory devices in electronic devices such as computers, smartphones, and tablets.
- Data storage systems in cloud computing and data centers.
Problems solved by this technology:
- Repairing failed columns in a memory cell array.
- Increasing the reliability and lifespan of memory devices.
Benefits of this technology:
- Improved memory device reliability by repairing failed columns.
- Extended lifespan of memory devices by utilizing redundancy columns.
- Cost-effective solution for memory repair without the need for complete replacement.
Original Abstract Submitted
A memory device includes a memory cell array having a plurality of memory cells therein that span a plurality of rows, which are grouped into segments, and a plurality of columns, which are grouped into ticks. The ticks include normal ticks, and a spare tick that spans at least one redundancy column of memory cells in the memory cell array. A repair circuit is provided, which is configured to: (i) repair a first source address of a first failed column, which spans a plurality of the segments, with a first destination address of a pass column in one of the normal ticks, and then (ii) further repair the first destination address of the pass column with a first redundancy column within the spare tick that corresponds to the first destination address.
