18296056. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Juhyeon Kim of Suwon-si (KR)

Ilhwan Kim of Suwon-si (KR)

Sunkyoung Seo of Suwon-si (KR)

Chajea Jo of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18296056 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The semiconductor package described in the patent application includes two semiconductor chips stacked on top of each other. The first chip has pads on its surface, while the second chip has pads on its front surface that are in contact with the pads on the first chip. The second chip also has through-electrodes with protruding portions on its rear surface. Through-via structures are placed around the second chip and are in contact with the pads on the first chip. A first dielectric layer covers the rear surface of the second chip and the side surfaces of the protruding portions of the through-electrodes. A second dielectric layer is below the first dielectric layer and fills the space between the protruding portions of the through-electrodes and the through-via structures. Bump structures are located below the second dielectric layer and are electrically connected to the through-electrodes and the through-via structures.

  • The semiconductor package includes two stacked semiconductor chips with pads and through-electrodes for electrical connections.
  • Through-via structures are used to connect the pads on the first chip to the pads on the second chip.
  • Dielectric layers are used to insulate and protect the through-electrodes and through-via structures.
  • Bump structures provide electrical connections between the through-electrodes and through-via structures.

Potential applications of this technology:

  • This semiconductor package design can be used in various electronic devices that require compact and efficient stacking of semiconductor chips.
  • It can be applied in mobile devices, such as smartphones and tablets, to save space and improve performance.

Problems solved by this technology:

  • The stacked design allows for more functionality in a smaller form factor, addressing the need for miniaturization in electronic devices.
  • The through-via structures provide reliable electrical connections between the stacked chips, ensuring proper signal transmission.

Benefits of this technology:

  • The compact size of the semiconductor package allows for more efficient use of space in electronic devices.
  • The through-via structures and bump structures provide reliable electrical connections, improving the overall performance and reliability of the semiconductor package.


Original Abstract Submitted

A semiconductor package includes: a first semiconductor chip including first pads; a second semiconductor chip below the first semiconductor chip, the second semiconductor chip including a substrate including a front surface and an opposing rear surface, second pads on the front surface and in contact with the first pads, and through-electrodes electrically connected to the second pads and including protruding portions protruding from the rear surface of the substrate; through-via structures disposed around the second semiconductor chip and in contact with the first pads; a first dielectric layer extending along the rear surface of the substrate and side surfaces of the protruding portions of the through-electrodes; a second dielectric layer below the first dielectric layer and in a space between the protruding portions of the through-electrodes and between the through-via structures; and bump structures below the second dielectric layer and electrically connected to the through-electrodes and the through-via structures.