18255037. SUBSTRATE FOR CARRYING WAFER simplified abstract (NIPPON TELEGRAPH AND TELEPHONE CORPORATION)
Contents
- 1 SUBSTRATE FOR CARRYING WAFER
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SUBSTRATE FOR CARRYING WAFER - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SUBSTRATE FOR CARRYING WAFER
Organization Name
NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Inventor(s)
Shoko Tatsumi of Musashino-shi, Tokyo (JP)
Masahiro Nada of Musashino-shi, Tokyo (JP)
Yasuhiko Nakanishi of Musashino-shi, Tokyo (JP)
SUBSTRATE FOR CARRYING WAFER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18255037 titled 'SUBSTRATE FOR CARRYING WAFER
Simplified Explanation
The present disclosure is for a wafer carrier substrate designed to carry a wafer with multiple chips, each containing elements to be measured. The substrate includes a vacuuming hole for securing the wafer, a wafer alignment guide for positioning the wafer correctly, and a mark for determining probe contact position.
- Vacuuming hole for securing the wafer
- Wafer alignment guide for correct positioning
- Mark for determining probe contact position
Potential Applications
This technology could be applied in semiconductor manufacturing processes where precise measurements of elements within chips are required.
Problems Solved
This innovation solves the issue of identifying specific shots on a semiconductor wafer without the need for additional processing.
Benefits
The wafer carrier substrate simplifies the measurement process by providing clear positioning and contact points for probes.
Potential Commercial Applications
This technology could be utilized in semiconductor fabrication facilities to improve efficiency and accuracy in chip testing processes.
Possible Prior Art
There may be prior art related to wafer carrier substrates with similar features for chip testing purposes.
Unanswered Questions
How does this technology compare to existing wafer carrier substrates in terms of accuracy and efficiency?
This article does not provide a direct comparison with existing technologies in the market.
Are there any limitations to the size or type of wafer that can be used with this substrate?
The article does not address any potential limitations regarding the size or type of wafers compatible with this substrate.
Original Abstract Submitted
The present disclosure is to provide a wafer carrier substrate for carrying a wafer on which a plurality of chips is formed, elements to be measured being built in the plurality of chips. The wafer carrier substrate includes: a vacuuming hole for vacuuming of the wafer placed on the wafer carrier substrate; a wafer alignment guide for determining a predetermined position of the wafer placed on the wafer carrier substrate; and a mark for determining a probe contact position. It is possible to recognize a specific shot, without any additional processing of the semiconductor wafer.
