18244069. MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE GATES simplified abstract (MICRON TECHNOLOGY, INC.)

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE GATES

Organization Name

MICRON TECHNOLOGY, INC.

Inventor(s)

Eric S. Carman of San Francisco CA (US)

Durai Vishak Nirmal Ramaswamy of Boise ID (US)

Richard E Fackenthal of Carmichael CA (US)

Kamal M. Karda of Boise ID (US)

Karthik Sarpatwari of Boise ID (US)

Haitao Liu of Boise ID (US)

Duane R. Mills of Shingle Springs CA (US)

Christian Caillat of Boise ID (US)

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE GATES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18244069 titled 'MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE GATES

Simplified Explanation

The patent application describes an apparatus and method for operating the apparatus, which includes a data line, a conductive region, and a memory cell with two transistors.

• The first transistor has a channel region connected to the data line and the conductive region, a charge storage structure, and a first gate.
• The second transistor has a channel region connected to the data line and the charge storage structure, and a second gate.
• The first gate is electrically separated from the second gate and positioned opposite to the second gate in a direction from the first channel region to the second channel region.

Potential applications of this technology:

• Memory devices: The described apparatus can be used in memory cells for storing and retrieving data.
• Data storage systems: This technology can be applied in various data storage systems, such as solid-state drives or flash memory.

Problems solved by this technology:

• Improved data storage: The described apparatus allows for efficient storage and retrieval of data in memory cells.
• Enhanced performance: The use of two transistors and separate gates improves the overall performance of the memory cell.

Benefits of this technology:

• Higher data density: The apparatus enables higher data density in memory cells, allowing for more efficient use of space.
• Faster data access: The improved design of the memory cell leads to faster data access and retrieval.
• Increased reliability: The separate gates and improved structure contribute to the overall reliability of the memory cell.

Original Abstract Submitted

Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.