18242628. MANUFACTURING METHOD OF INTEGRATED CIRCUIT DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

MANUFACTURING METHOD OF INTEGRATED CIRCUIT DEVICE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Sungwoon Hwang of Suwon-si (KR)

Dongryul Chang of Suwon-si (KR)

Byoungchul Park of Suwon-si (KR)

Hyesoo Park of Suwon-si (KR)

Sungrey Wi of Suwon-si (KR)

Yunjoo Lee of Suwon-si (KR)

Kwangil Choi of Suwon-si (KR)

Jaesang Choi of Suwon-si (KR)

Hayeong Choi of Suwon-si (KR)

Soonchoel Her of Suwon-si (KR)

MANUFACTURING METHOD OF INTEGRATED CIRCUIT DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18242628 titled 'MANUFACTURING METHOD OF INTEGRATED CIRCUIT DEVICE

Simplified Explanation

The method described in the abstract involves manufacturing an integrated circuit device by forming dummy gates and gate spaces on a substrate. Here are the key points of the method:

• Form dummy gate insulating layer on active regions of the substrate
• Create dummy gates on the active regions
• Apply inter-gate insulating layer over the dummy gates
• Remove dummy gates to form gate spaces
• Add extra gate insulating layer in exposed areas
• Remove portions of insulating layer to define gate spaces
• Form gate insulating layer and gate electrode in the gate spaces

Potential Applications: - Semiconductor manufacturing - Integrated circuit fabrication - Electronics industry

Problems Solved: - Efficient manufacturing of integrated circuit devices - Precise formation of gate structures - Improved performance of electronic devices

Benefits: - Higher quality integrated circuit devices - Enhanced functionality of electronic components - Increased productivity in semiconductor production

Original Abstract Submitted

A method of manufacturing an integrated circuit device includes forming a dummy gate insulating layer on first to third active regions of a substrate, forming first to third dummy gates on the first to third active regions, respectively, forming an inter-gate insulating layer covering the first to third dummy gates, forming a third gate space by removing the third dummy gate while the first and second dummy gates are covered, forming an extra gate insulating layer on the dummy gate insulating layer exposed to the third gate space, forming first and second gate spaces by removing the first and second dummy gates while the third dummy gate is covered, removing a first portion of the dummy gate insulating layer exposed to the first gate space while the second and third gate spaces are covered, and forming a gate insulating layer and a gate electrode in the gate spaces.