18239241. SEMICONDUCTOR DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18239241 titled 'SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a semiconductor device that includes an active pattern with a channel region. The channel region connects two source/drain patterns and is located between them. A gate electrode is positioned on the bottom surface of the active pattern, between the source/drain patterns. An upper interconnection line is placed on the top surface of the active pattern and is connected to one of the source/drain patterns.
- The semiconductor device has an active pattern with a channel region that connects two source/drain patterns.
- A gate electrode is positioned on the bottom surface of the active pattern, between the source/drain patterns.
- An upper interconnection line is placed on the top surface of the active pattern and is connected to one of the source/drain patterns.
Potential Applications
This technology can be applied in various fields, including:
- Integrated circuits
- Microprocessors
- Memory devices
- Power devices
Problems Solved
The semiconductor device described in the patent application solves several problems, such as:
- Efficiently connecting source/drain patterns with a channel region
- Providing a compact and space-saving design
- Enhancing the performance and functionality of integrated circuits
Benefits
The use of this technology offers several benefits, including:
- Improved connectivity and functionality of semiconductor devices
- Enhanced performance and efficiency of integrated circuits
- Compact and space-saving design for semiconductor devices
Original Abstract Submitted
A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.
