18239140. SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUIT simplified abstract (Kioxia Corporation)

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SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUIT

Organization Name

Kioxia Corporation

Inventor(s)

Hiroshi Maejima of Tokyo (JP)

SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUIT - A simplified explanation of the abstract

This abstract first appeared for US patent application 18239140 titled 'SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUIT

Simplified Explanation

The patent application describes a memory device with multiple memory cells and sense amplifiers arranged in a specific configuration.

  • The memory device includes multiple memory cells provided above a substrate.
  • Each memory cell is connected to a corresponding bit line that extends in a first direction.
  • Sense amplifiers are used to sense the voltage of each bit line.
  • The sense amplifiers are arranged in groups, with the first and second sense amplifiers belonging to the first group and the third sense amplifier belonging to the second group.
  • The first and second sense amplifiers are adjacent to each other and arranged in a second direction that intersects the first direction.
  • The first and second sense amplifier groups are adjacent to each other and arranged in the first direction.

Potential applications of this technology:

  • Memory devices used in various electronic devices such as computers, smartphones, and tablets.
  • Data storage systems in cloud computing and data centers.
  • Embedded memory in microcontrollers and other integrated circuits.

Problems solved by this technology:

  • Efficient sensing of the voltage in multiple bit lines.
  • Improved organization and arrangement of sense amplifiers for better performance and reliability.
  • Reduction of signal interference and crosstalk between adjacent bit lines.

Benefits of this technology:

  • Higher memory density and capacity.
  • Faster and more reliable data access and retrieval.
  • Improved overall performance and efficiency of memory devices.
  • Enhanced signal integrity and reduced noise interference.


Original Abstract Submitted

A memory device includes a first memory cell provided above a substrate; a first bit line coupled to the first memory cell and extending in a first direction; a first sense amplifier configured to sense a voltage of the first bit line; a second memory cell provided above the substrate; a second bit line adjacent to the first bit line and extending in the first direction, the second bit line being coupled to the second memory cell; a second sense amplifier configured to sense a voltage of the second bit line; and a third memory cell provided above the substrate. A third bit line not adjacent to the second bit line extends in the first direction, and is coupled to the third memory cell; and a third sense amplifier is configured to sense a voltage of the third bit line. The first and second sense amplifiers belong to a first sense amplifier group, are adjacent to each other and are arranged in a second direction intersecting the first direction. The third sense amplifier belongs to a second sense amplifier group. The first and second sense amplifier groups are adjacent to each other and are arranged in the first direction.

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