18236566. INTEGRATION OF MEMORY ARRAY WITH PERIPHERY simplified abstract (Micron Technology, Inc.)
Contents
INTEGRATION OF MEMORY ARRAY WITH PERIPHERY
Organization Name
Inventor(s)
Shivani Srivastava of Boise ID (US)
Russell Allen Benson of Boise ID (US)
Raghunath Singanamalla of Boise ID (US)
Jaydeb Goswami of Boise ID (US)
INTEGRATION OF MEMORY ARRAY WITH PERIPHERY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18236566 titled 'INTEGRATION OF MEMORY ARRAY WITH PERIPHERY
Simplified Explanation
The patent application describes an apparatus with a memory device structured from integrated processing of a memory array with a periphery, where transistors in the periphery are formed without polysilicon regions between the metal gates and metal contacts.
- Memory device implemented with transistors in the periphery
- Metal gates of transistors structured without polysilicon regions
- Integrated processing provides step height reduction between memory array and periphery
- Elimination of polysilicon on gate stack of transistors in the periphery
- Step height reduction lowers overlap capacitance
Potential Applications
- Semiconductor manufacturing
- Memory devices
- Integrated circuits
Problems Solved
- Reduced step height between memory array and periphery
- Lower overlap capacitance
- Improved performance of memory devices
Benefits
- Enhanced efficiency in semiconductor manufacturing
- Improved performance and reliability of memory devices
- Cost-effective production of integrated circuits
Original Abstract Submitted
A variety of applications can include apparatus having a memory device structured from integrated processing of a memory array of the memory device with a periphery to the memory array. The memory device can be implemented with transistors formed in the periphery, where metal gates of the transistors are structured without polysilicon regions between the metal gates and metal contacts for the metal gates. The integrated processing can provide step height reduction between the memory array and the periphery to the memory array of a memory device, with the elimination of polysilicon on the gate stack of transistors in the periphery. The step height reduction in the memory device can lower overlap capacitance.
