18234633. Pseudo Lock-Step Execution Across CPU Cores simplified abstract (Google LLC)
Contents
- 1 Pseudo Lock-Step Execution Across CPU Cores
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Pseudo Lock-Step Execution Across CPU Cores - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
Pseudo Lock-Step Execution Across CPU Cores
Organization Name
Inventor(s)
Balaram Sinharoy of Cupertino CA (US)
Peter Hochschild of New York NY (US)
Pseudo Lock-Step Execution Across CPU Cores - A simplified explanation of the abstract
This abstract first appeared for US patent application 18234633 titled 'Pseudo Lock-Step Execution Across CPU Cores
Simplified Explanation
The present disclosure describes a method for automatically detecting errors, such as SDC, in a multi-core computing environment by running cores in an error detection mode where multiple cores repeat the same execution of instructions and compare the results to determine if one of the cores is failing.
- Cores in a multi-core computing environment run in an error detection mode.
- Multiple cores repeat the same execution of instructions.
- The results of the instructions are compared to detect errors, such as SDC.
- Based on the results, it is determined whether one of the cores is failing.
Potential Applications
This technology could be applied in:
- High-performance computing systems
- Data centers
- Cloud computing environments
Problems Solved
This technology helps in:
- Detecting errors, such as SDC, in multi-core computing environments
- Improving system reliability and performance
Benefits
The benefits of this technology include:
- Enhanced error detection capabilities
- Improved system reliability
- Increased performance efficiency
Potential Commercial Applications
This technology could be used in:
- Server systems
- Supercomputers
- Mission-critical applications
Possible Prior Art
One possible prior art for this technology could be:
- Error detection mechanisms in single-core computing systems
Unanswered Questions
How does this technology impact power consumption in multi-core computing environments?
This article does not address the potential impact of this technology on power consumption in multi-core computing environments.
Are there any limitations to the scalability of this error detection method in large-scale computing systems?
The article does not discuss any limitations to the scalability of this error detection method in large-scale computing systems.
Original Abstract Submitted
The present disclosure provides for automatically detecting errors, such as SDC, in a multi-core computing environment. For example, cores may run in an error detection mode, in which multiple cores repeat the same execution of instructions and the results are compared. Based on the results, it may be determined whether one of the cores is failing.
