18232568. VERTICAL MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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VERTICAL MEMORY DEVICE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Sohyeon Lee of Suwon-si (KR)

Seahoon Lee of Suwon-si (KR)

Jaeduk Lee of Suwon-si (KR)

Tackhwi Lee of Suwon-si (KR)

VERTICAL MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232568 titled 'VERTICAL MEMORY DEVICE

Simplified Explanation

The abstract describes a vertical memory device with specific sub-semiconductor patterns and common source contacts. The device includes a substrate with two regions of different widths, each covered by a sub-semiconductor pattern with varying thicknesses. The common source contacts are located on the edges of the patterns.

  • The device includes a substrate with two regions of different widths.
  • Sub-semiconductor patterns cover each region with varying thicknesses.
  • Common source contacts are located on the edges of the patterns.

Potential Applications

This technology could be applied in:

  • Memory devices
  • Semiconductor manufacturing

Problems Solved

This technology helps address:

  • Efficient use of space on a substrate
  • Enhanced performance of memory devices

Benefits

The benefits of this technology include:

  • Improved memory device performance
  • Optimal use of substrate space

Potential Commercial Applications

A potential commercial application for this technology could be in:

  • Memory chip manufacturing

Possible Prior Art

One possible prior art for this technology could be:

  • Vertical memory devices with common source contacts

Unanswered Questions

How does this technology compare to existing memory devices?

This article does not provide a direct comparison to existing memory devices, leaving the reader to wonder about the specific advantages of this new technology.

What are the specific manufacturing processes involved in creating this vertical memory device?

The article does not delve into the detailed manufacturing processes involved in creating this vertical memory device, leaving the reader curious about the specific steps and techniques used.


Original Abstract Submitted

A vertical memory device includes a substrate, first and second sub-semiconductor patterns, first and second common source contacts, and first and second cell structures. The substrate includes a first region and a second region having a same length as the first region in a first direction, the first region having a first width in a second direction perpendicular to the first direction, and the second region having a second width in the second direction that is less than the first width. The first sub-semiconductor pattern covers the first region, and a portion of the first sub-semiconductor pattern has a first thickness. The second sub-semiconductor pattern covers the second region and has a second thickness that is less than the first thickness. The first and second common source contacts are disposed on edges in the second direction of the first and second patterns, respectively.