18229981. MEMORY QUEUE OPERATIONS TO INCREASE THROUGHPUT IN AN ATE SYSTEM simplified abstract (ADVANTEST CORPORATION)

MEMORY QUEUE OPERATIONS TO INCREASE THROUGHPUT IN AN ATE SYSTEM

Organization Name

ADVANTEST CORPORATION

Inventor(s)

Edmundo De La Puente of San Jose CA (US)

Srdjan Malisic of San Jose CA (US)

MEMORY QUEUE OPERATIONS TO INCREASE THROUGHPUT IN AN ATE SYSTEM - A simplified explanation of the abstract

This abstract first appeared for US patent application 18229981 titled 'MEMORY QUEUE OPERATIONS TO INCREASE THROUGHPUT IN AN ATE SYSTEM

Simplified Explanation

The tester system described in the abstract is a system that coordinates and controls the testing of multiple devices under test (DUTs) using a hardware interface board. The hardware interface board is responsible for applying test input signals to the DUTs and receiving test output signals from them. It includes a processor, memory with FIFO memory queue, DMA engine, buffer table, and driver hardware.

• Processor for accessing test pattern data
• Memory with FIFO memory queue for organizing test pattern data
• DMA engine for reading data from memory and supplying it to DUTs
• Buffer table for maintaining buffer sequence and vacancy/occupancy information
• Driver hardware for driving test input signals to DUTs

Potential Applications

The technology described in the patent application could be applied in various industries such as electronics manufacturing, telecommunications, automotive, and aerospace for testing and quality control of electronic devices.

Problems Solved

This technology solves the problem of efficiently coordinating and controlling the testing of multiple devices simultaneously, ensuring accurate and reliable test results.

Benefits

The benefits of this technology include increased testing efficiency, improved accuracy of test results, and streamlined testing processes for complex electronic devices.

Potential Commercial Applications

The potential commercial applications of this technology include test equipment manufacturing, electronic device manufacturing, quality control services, and research and development laboratories.

Possible Prior Art

One possible prior art for this technology could be automated test equipment (ATE) systems used in the electronics industry for testing electronic components and devices.

How does the system handle errors during testing?

The abstract does not provide information on how the system handles errors that may occur during the testing process. It would be important to know how the system detects and addresses errors to ensure the reliability of test results.

What is the scalability of the system for testing a large number of DUTs?

The abstract does not mention the scalability of the system for testing a large number of devices under test. Understanding the system's capacity and limitations in handling a high volume of DUTs would be crucial for industries with large-scale testing requirements.

Original Abstract Submitted

A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs), and a hardware interface board coupled to the test computer system and controlled by the test computer system. The hardware interface board is operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs, the hardware interface board including: a processor operable to access test pattern data for application to a DUT. The tester system also includes a memory coupled to the processor and including a plurality of buffers, the plurality of buffers organized into a first-in-first-out (FIFO) memory queue including a buffer front end and a buffer back end, the plurality of buffers operable to receive the test pattern data from the processor at the buffer front end, a direct memory access (DMA) engine coupled to the memory and operable for reading data out of the buffer back end and supplying test pattern data to the DUT, a buffer table for maintaining a buffer sequence within the plurality of buffers and for maintaining vacancy and occupancy information regarding the plurality of buffers, and driver hardware coupled to the DMA engine and operable to receive the test pattern data and for driving the test input signals to the plurality of DUTs.