18220734. SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS simplified abstract (Micron Technology, Inc.)

SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS

Organization Name

Micron Technology, Inc.

Inventor(s)

Kyle K. Kirby of Eagle ID (US)

Bret K. Street of Meridian ID (US)

Bang-Ning Hsu of Taichung (TW)

SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18220734 titled 'SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS

Simplified Explanation

• • Explanation:**

The patent application discloses semiconductor devices and assemblies that include multiple die packages stacked on top of each other, each containing different components such as active cells, CMOS circuitry, and backend of line circuitry.

• • Bullet Points:**
• Semiconductor device with multiple stacked die packages
• Each package contains different components such as active cells, CMOS circuitry, and backend of line circuitry
• Interconnect portion on one die connects components on another die
• Hybrid bonding used to attach dies together

• • Potential Applications:**
• High-performance computing
• Data storage devices
• Mobile devices
• Internet of Things (IoT) devices

• • Problems Solved:**
• Increased integration of components in a compact space
• Improved performance and efficiency of semiconductor devices
• Enhanced functionality and capabilities of electronic devices

• • Benefits:**
• Higher processing power in a smaller form factor
• Improved energy efficiency
• Enhanced functionality and features in electronic devices

Original Abstract Submitted

Semiconductor devices and semiconductor device assemblies, and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a support substrate, a first die package carried by the support substrate, and a second die package carried by the first die package. Each of the first and second die packages can include a first die, a second die hybrid bonded a surface of the first die, and a third die hybrid bonded to a surface of the second die. The first die is coupled to the third die via an interconnect portion of the second die. Further, the third die can include an array of active cells for each of the packages, the second die can include complementary-metal-oxide-semiconductor (CMOS) circuitry accessing the active cells, and the first die can include backend of line (BEOL) circuitry associated with the active cells and CMOS circuitry.