18220536. Performance Optimized Task Duplication and Migration simplified abstract (GOOGLE LLC)
Contents
Performance Optimized Task Duplication and Migration
Organization Name
Inventor(s)
Jonathan Charles Masters of Boston MA (US)
Performance Optimized Task Duplication and Migration - A simplified explanation of the abstract
This abstract first appeared for US patent application 18220536 titled 'Performance Optimized Task Duplication and Migration
Simplified Explanation
The technology described in the patent application enables the duplication of micro-architectural context information when a running application is cloned, migrated, or persisted into secondary storage.
- Extract microarchitectural information from a processing element.
- Transfer the extracted information to an operating system.
- Forward the information to another processing element.
- Instantiate a process at the second processing element using the extracted information.
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- Potential Applications
- Cloud computing
- Virtualization technology
- High-performance computing
- Problems Solved
- Faster function start-up for cloned applications
- Efficient migration of applications between cores or machines
- Improved persistence of application state
- Benefits
- Reduced start-up time for applications
- Enhanced performance in virtualized environments
- Improved resource utilization in high-performance computing systems
Original Abstract Submitted
Aspects of the technology are directed to methods and systems that enable duplication of micro-architectural context information when a running application is cloned (e.g., for a faster function start up), migrated (e.g., to another core or machine), or persisted into secondary storage. The method, for example, may comprise extracting microarchitectural information from a first processing element, transferring the extracted microarchitectural information to a first operating system, forwarding, by the first operating system, the extracted microarchitectural information to a second processing element, and instantiating a process at the second processing element using the extracted microarchitectural information.
