18217924. GATE DRIVER AND DISPLAY APPARATUS INCLUDING SAME simplified abstract (Samsung Display Co., LTD.)
GATE DRIVER AND DISPLAY APPARATUS INCLUDING SAME
Organization Name
Inventor(s)
Nackhyeon Keum of Yongin-si (KR)
Kimyeong Eom of Yongin-si (KR)
Kwangsae Lee of Yongin-si (KR)
GATE DRIVER AND DISPLAY APPARATUS INCLUDING SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18217924 titled 'GATE DRIVER AND DISPLAY APPARATUS INCLUDING SAME
Simplified Explanation
- The gate driver described in the patent application consists of multiple stages, each containing an output unit with a pull-up transistor and a pull-down transistor. - The driver includes a second node controller that manages the voltage of a second control node connected to the gate of the pull-up transistor. - The second node controller comprises a first control transistor linked between the first clock terminal and the second control node, with its gate connected to the first control node. - Additionally, the second node controller features a second control transistor with its gate connected to the gate of the first control transistor, regulating a short circuit between the first clock terminal and a second clock terminal.
Potential Applications
- Power electronics - Motor control systems - Renewable energy systems
Problems Solved
- Efficiently controlling the voltage of the second control node - Ensuring proper functioning of the pull-up and pull-down transistors in the gate driver
Benefits
- Improved performance and reliability of gate drivers - Enhanced control over power electronics systems - Increased efficiency in motor control and renewable energy applications
Original Abstract Submitted
Provided is a gate driver including a plurality of stages, wherein each stage includes an output unit including a pull-up transistor and a pull-down transistor, and a second node controller configured to control a voltage of a second control node to which a gate of the pull-up transistor is connected, wherein the second node controller includes a first control transistor connected between the first clock terminal and the second control node and including a gate connected to the first control node, and a second control transistor including a gate connected to the gate of the first control transistor and configured to control a short circuit between the first clock terminal and a second clock terminal.
