18217701. SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
Organization Name
Inventor(s)
Young Kun Jee of Suwon-si (KR)
Un-Byoung Kang of Suwon-si (KR)
Jum Yong Park of Suwon-si (KR)
Jong-Hyeon Chang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18217701 titled 'SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
Simplified Explanation
The semiconductor package described in the patent application includes a redistribution substrate, a first semiconductor chip, a second semiconductor chip, and a filling insulating film.
- The first semiconductor chip is placed on the redistribution substrate and has a first semiconductor substrate, first through vias that penetrate through the substrate, and a first bonding layer on the substrate. The first bonding layer is electrically connected to the first through vias.
- The second semiconductor chip has a second semiconductor substrate and a second bonding layer on the substrate. The second bonding layer is bonded to the first bonding layer.
- A filling insulating film is applied on the redistribution substrate, covering both the first and second semiconductor chips. The upper surface of the filling insulating film is positioned above the upper surfaces of both semiconductor chips.
Potential applications of this technology:
- This semiconductor package design can be used in various electronic devices that require multiple semiconductor chips to be integrated into a compact package.
- It can be applied in mobile devices, such as smartphones and tablets, to enhance their performance and functionality.
- It can also be used in automotive electronics, medical devices, and other industries where miniaturization and integration of semiconductor chips are crucial.
Problems solved by this technology:
- The semiconductor package solves the problem of limited space by allowing multiple semiconductor chips to be stacked and interconnected in a compact package.
- It provides a reliable electrical connection between the semiconductor chips through the bonding layers and through vias, ensuring efficient data transfer and signal processing.
Benefits of this technology:
- The semiconductor package offers improved performance and functionality by integrating multiple semiconductor chips in a small form factor.
- It enables higher levels of integration, reducing the overall size and weight of electronic devices.
- The design provides a more efficient and reliable electrical connection between the semiconductor chips, enhancing the overall performance and reliability of the package.
Original Abstract Submitted
A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding layer disposed on the first semiconductor substrate. The first bonding layer is electrically connected to the first through vias. A second semiconductor chip includes a second semiconductor substrate and a second bonding layer disposed on the second semiconductor substrate. The second bonding layer is bonded to the first bonding layer. A filling insulating film is disposed on the redistribution substrate. The filling insulating film covers the first semiconductor chip and the second semiconductor chip. An upper surface of the filling insulating film is disposed on a level above an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip.
