18217655. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18217655 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract of the patent application describes a semiconductor package that includes multiple chips and an interposer chip. The interposer chip has a through-via that electrically connects the upper chip to the substrate. The first lower semiconductor chip is electrically connected to the upper chip, and its lower surface is disposed on the upper surface of the first lower semiconductor chip. Similarly, the second lower semiconductor chip is electrically connected to the upper chip, and its lower surface is disposed on the upper surface of the second lower semiconductor chip.
- The semiconductor package includes a substrate, upper chip, and multiple lower semiconductor chips.
- An interposer chip is placed between the substrate and the upper chip.
- The interposer chip has a through-via that connects the upper chip to the substrate.
- The first lower semiconductor chip is electrically connected to the upper chip.
- The second lower semiconductor chip is also electrically connected to the upper chip.
- The lower surfaces of the upper chip are disposed on the upper surfaces of the lower semiconductor chips.
Potential applications of this technology:
- Semiconductor packaging for electronic devices.
- Integration of multiple chips in a compact and efficient manner.
- Improved electrical connectivity between chips.
Problems solved by this technology:
- Efficient electrical connection between multiple chips.
- Space-saving packaging design.
- Enhanced performance and functionality of electronic devices.
Benefits of this technology:
- Compact and efficient integration of multiple chips.
- Improved electrical connectivity and signal transmission.
- Cost-effective semiconductor packaging solution.
Original Abstract Submitted
A semiconductor package may include: a substrate; an upper chip disposed on the substrate; a first lower semiconductor chip disposed between the substrate and the upper chip, and electrically connected to the substrate; a second lower semiconductor chip disposed between the substrate and the upper chip, and electrically connected to the substrate; and an interposer chip disposed between the substrate and the upper chip, wherein the interposer chip includes a through-via electrically connecting the upper chip to the substrate, wherein the first lower semiconductor chip is electrically connected to the upper chip, wherein a lower surface of the upper chip is disposed on an upper surface of the first lower semiconductor chip, and wherein the second lower semiconductor chip is electrically connected to the upper chip, wherein a lower surface of the upper chip is disposed on an upper surface of the second lower semiconductor chip.
