18216632. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18216632 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a redistribution wiring layer with redistribution wirings stacked in at least two levels, a first semiconductor chip, multiple second semiconductor chips, conductive wires connecting chip pads to the redistribution wirings, and a sealing unit.
- The semiconductor package has redistribution wirings stacked in at least two levels.
- It includes a first semiconductor chip placed on the redistribution wiring layer.
- Multiple second semiconductor chips are arranged on the first semiconductor chip.
- Conductive wires connect the chip pads of the first semiconductor chip to the redistribution wirings.
- Additional conductive wires connect the chip pads of the second semiconductor chips to the redistribution wirings.
- A sealing unit is placed on top of the redistribution wiring layer.
Potential applications of this technology:
- Advanced electronic devices
- Integrated circuits
- Microprocessors
Problems solved by this technology:
- Improved connectivity between semiconductor chips
- Enhanced performance of electronic devices
- Increased efficiency in data transfer
Benefits of this technology:
- Higher functionality in semiconductor packages
- Enhanced reliability in electronic systems
- Improved overall performance of electronic devices
Original Abstract Submitted
A semiconductor package includes a redistribution wiring layer having redistribution wirings stacked in at least two levels; a first semiconductor chip arranged on the redistribution wiring layer; a plurality of second semiconductor chips arranged on the first semiconductor chip; first conductive wires electrically connecting first chip pads of the first semiconductor chip and the redistribution wirings of the redistribution wiring layer; second conductive wires electrically connecting second chip pads of the plurality of second semiconductor chips and the redistribution wirings of the redistribution wiring layer; and a sealing unit disposed on the redistribution wiring layer.
