18212939. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Kyounglim Suk of Suwon-si (KR)
Hyeonjeong Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18212939 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a complex structure involving multiple layers and components to enhance the performance and reliability of semiconductor chips. Here are some key points to explain the patent/innovation:
- The package consists of a first redistribution structure with at least one redistribution layer and one insulating layer.
- A first semiconductor chip is electrically connected to the redistribution layer and placed on the first surface of the redistribution structure.
- A second semiconductor chip is positioned on top of the first semiconductor chip.
- A first encapsulant is located on the second surface of the redistribution structure, opposite the first surface.
- First conductive posts connect the first semiconductor chip and penetrate the encapsulant.
- Under bump metallurgy (UBM) structures are situated on the lower surface of the encapsulant, overlapping with the first conductive posts and connected to them.
Potential Applications: The technology described in this patent application could be utilized in various semiconductor devices, such as microprocessors, memory chips, and sensors, to improve electrical connections and thermal management.
Problems Solved: This technology addresses challenges related to electrical connectivity, thermal dissipation, and overall reliability in semiconductor packaging, ensuring stable performance under different operating conditions.
Benefits: By incorporating advanced structures and materials, this technology enhances the functionality and longevity of semiconductor devices, leading to improved performance and durability.
Potential Commercial Applications of this Technology:
- Enhancing the performance and reliability of consumer electronics, automotive systems, and industrial equipment.
- Enabling the development of high-speed communication devices and advanced computing systems.
Possible Prior Art: There may be prior art related to semiconductor packaging techniques involving redistribution layers, encapsulants, and conductive posts. Previous patents or publications in the field of semiconductor packaging could provide insights into similar approaches or technologies.
Unanswered Questions: 1. How does the overlap between the UBM structures and conductive posts impact the overall electrical performance of the semiconductor package? 2. Are there any specific manufacturing processes or materials used in this technology that differentiate it from existing semiconductor packaging methods?
Original Abstract Submitted
A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.
