18212461. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Raeyoung Kang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18212461 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The semiconductor package described in the patent application includes two semiconductor chips, with the second chip stacked on top of the first chip and connected through a wiring structure.
- The first semiconductor chip has a through-electrode passing through its semiconductor layer in a vertical direction, with a bonding pad connected to the through-electrode.
- The second semiconductor chip has a wiring structure connecting its semiconductor layer to the first chip, with a wiring pad and a bonding pad connected in series below the wiring pad.
- The second bonding pad on the second chip includes a protrusion that extends towards the wiring pad, ensuring a secure connection between the two chips.
Potential Applications
- This technology could be used in advanced semiconductor devices such as microprocessors, memory chips, and sensors.
- It could also be applied in high-performance computing, telecommunications, and automotive electronics.
Problems Solved
- Enables efficient stacking of multiple semiconductor chips in a compact package.
- Provides a reliable and high-speed connection between stacked chips.
- Reduces signal interference and improves overall performance of the semiconductor package.
Benefits
- Increased functionality and performance of semiconductor devices.
- Enhanced reliability and durability of stacked chip packages.
- Cost-effective manufacturing process for complex semiconductor assemblies.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode passing through the first semiconductor layer in a vertical direction, and a first bonding pad connected to the first through-electrode, and a second semiconductor chip including a second semiconductor layer on the first semiconductor chip, a wiring structure between the second semiconductor layer and the first semiconductor chip, a wiring pad connected to the wiring structure below the wiring structure, and a second bonding pad connected to the wiring pad below the wiring pad and in contact with the first bonding pad, wherein the second bonding pad includes a protrusion protruding toward the wiring pad.
