18209820. SEMICONDUCTOR DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Joongwon Shin of Suwon-si (KR)
SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18209820 titled 'SEMICONDUCTOR DEVICE
Simplified Explanation
The semiconductor device described in the patent application includes multiple layers of metal wirings and insulating interlayers, as well as an oxide layer for supplying hydrogen.
- Lower metal wirings are stacked in multiple layers on a substrate.
- The device includes upper insulating interlayers and metal patterns.
- An oxide layer is present on the uppermost insulating interlayer for supplying hydrogen.
- The uppermost via has a thickness less than 40% of the uppermost metal pattern.
---
- Potential Applications
- This technology can be used in the manufacturing of advanced semiconductor devices for various electronic applications.
- Problems Solved
- This technology helps in improving the performance and reliability of semiconductor devices by providing a more efficient structure for metal wirings and insulating layers.
- Benefits
- Enhanced performance and reliability of semiconductor devices.
- Improved efficiency in metal wiring and insulating layer structures.
- Potential for increased functionality and miniaturization in electronic devices.
Original Abstract Submitted
A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.
