18202735. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18202735 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a method of manufacturing a semiconductor package with multiple layers of redistribution wiring, a semiconductor device mounted on the wiring layer, a sealing member covering the device, conductive connectors for electrical connection, and heat transfer plugs for thermal management.
- First redistribution wiring layer with chip mounting region and peripheral region
- Multiple layers of redistribution wires stacked in the wiring layer
- Semiconductor device mounted on chip mounting region
- Sealing member covering the semiconductor device
- Conductive connectors on peripheral region for electrical connection
- Through openings on chip mounting region filled with conductive material to form heat transfer plugs
Potential Applications
- Semiconductor packaging industry
- Electronics manufacturing
- Thermal management solutions
Problems Solved
- Efficient electrical connection in semiconductor packages
- Improved thermal management for semiconductor devices
- Enhanced reliability and performance of electronic components
Benefits
- Increased functionality and performance of semiconductor packages
- Better heat dissipation for semiconductor devices
- Enhanced reliability and longevity of electronic products
Original Abstract Submitted
There is provided a method of manufacturing a semiconductor package, a first redistribution wiring layer including a chip mounting region and a peripheral region surrounding the chip mounting region is formed, and the first redistribution wiring layer has first redistribution wires stacked in at least two layers. A first semiconductor device is mounted on the chip mounting region on the first redistribution wiring layer. A sealing member is formed on the first redistribution wiring layer to cover the first semiconductor device. A plurality of conductive connectors is formed on the peripheral region, and the conductive connectors penetrate the sealing member and are electrically connected to the first redistribution wires. A plurality of through openings extending from an upper surface of the sealing member is formed on the chip mounting region and exposes an upper surface of the first semiconductor device. The through openings are filled up with a conductive material to form a plurality of heat transfer plugs.
