18202019. THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Seung Yoon Kim of Suwon-si (KR)
Byoung Jae Park of Suwon-si (KR)
Jae-Hwang Sim of Suwon-si (KR)
THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18202019 titled 'THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
Simplified Explanation
The abstract describes a three-dimensional semiconductor device with various structures such as source structure, gate stacking structure, insulating structure, memory channel structure, separation structure, and penetration plug.
- Source structure with cell region and extension region
- Gate stacking structure with insulating patterns and conductive patterns
- Insulating structure with multiple insulating layers
- Memory channel structure connected to the cell region
- Separation structure extending from cell region to extension region
- Penetration plug with first and second plug portions
- Separation structure with first and second separation portions
- Potential Applications:**
- Memory devices
- Semiconductor manufacturing
- Three-dimensional integrated circuits
- Problems Solved:**
- Improved performance and efficiency of semiconductor devices
- Enhanced connectivity and functionality in three-dimensional structures
- Benefits:**
- Higher memory capacity
- Increased speed and reliability
- More compact and efficient semiconductor devices
Original Abstract Submitted
A three-dimensional semiconductor device includes: a source structure including a cell region and an extension region; a gate stacking structure disposed on the source structure, the gate stacking structure including insulating patterns and conductive patterns, which are alternately stacked on each other; an insulating structure disposed on the gate stacking structure, the insulating structure including a plurality of insulating layers; a memory channel structure penetrating the gate stacking structure and electrically connected to the cell region; a separation structure penetrating the gate stacking structure and extending from the cell region to the extension region; and a penetration plug penetrating the gate stacking structure and the extension region, wherein the penetration plug includes: a first plug portion penetrating the gate stacking structure; and a second plug portion on the first plug portion, wherein the separation structure includes: a first separation portion penetrating the gate stacking structure; and a second separation portion on the first separation portion, and wherein a top surface of the first plug portion and a top surface of the first separation portion are at a substantially same level.
