18197768. SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Woo Sung Yang of Suwon-si (KR)
Suk Kang Sung of Suwon-si (KR)
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18197768 titled 'SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
Simplified Explanation
The semiconductor device described in the patent application includes two substrates connected to each other, with one substrate having a plate layer with gate electrode layers and channel structures, while the other substrate has via structures and via connecting structures.
- The device has gate electrode layers on a plate layer, with channel structures extending through them.
- Word-line cutting structures are spaced apart through the gate electrode layers.
- Via structures are on the other side of the plate layer, with via connecting structures on top of them.
- The bottom face of the via structures is wider than the top face, and the bottom face of the via connecting structures is narrower than the top face.
Potential applications of this technology:
- Semiconductor manufacturing
- Integrated circuits
- Memory devices
Problems solved by this technology:
- Efficient connection between substrates
- Improved performance of semiconductor devices
- Enhanced reliability of electronic components
Benefits of this technology:
- Higher integration density
- Better signal transmission
- Increased overall device performance
Original Abstract Submitted
A semiconductor device includes first and second substrates connected to each other. The second substrate includes a plate layer having first and second faces. Gate electrode layers are disposed on the first face of the plate layer. Channel structures extend through the gate electrode layers. Word-line cutting structures extend through the gate electrode layers and are spaced apart from each other. Via structures are disposed on the second face of the plate layer. Via connecting structures are disposed on the top face of the via structures. A width of the bottom face of each of the via structures is greater than a width of the top face of each of the via structures. A width of the bottom face of each of the via connecting structures is less than a width of the top face of each of the via connecting structures.
