18196309. TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE simplified abstract (Intel Corporation)

TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE

Organization Name

Intel Corporation

Inventor(s)

BINATA Bhattacharyya of Hillsboro OR (US)

PAUL S. Diefenbaugh of Portland OR (US)

TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18196309 titled 'TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE

Simplified Explanation

The abstract describes techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. These techniques involve disabling one or more memory channels during the reduced power state by mapping memory usages to different memory channels.

• The computer identifies low-power mode blocks within its functional blocks.
• The computer has a processor, memory, and multiple memory channels.
• Usage of the low-power mode blocks is mapped to a specific address range associated with a particular memory channel.

Potential applications of this technology:

• Power-efficient video playback on computers.
• Improved performance during connected standby mode.
• Enhanced power management in various computing devices.

Problems solved by this technology:

• Reducing power consumption during specific computer states.
• Optimizing memory access for improved performance.
• Managing power usage in a more efficient manner.

Benefits of this technology:

• Extended battery life for portable devices.
• Enhanced performance during specific computer states.
• Improved power management capabilities.

Original Abstract Submitted

Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.