18195749. SEMICONDUCTOR DEVICES simplified abstract (Samsung Electronics Co., Ltd.)

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SEMICONDUCTOR DEVICES

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Younggwon Kim of Suwon-si (KR)

Myunggil Kang of Suwon-si (KR)

Dongwon Kim of Suwon-si (KR)

Beomjin Park of Suwon-si (KR)

Inu Jeon of Suwon-si (KR)

Soojin Jeong of Suwon-si (KR)

SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18195749 titled 'SEMICONDUCTOR DEVICES

Simplified Explanation

The semiconductor device described in the abstract includes:

  • A substrate with an active region extending in one direction
  • A gate electrode layer crossing the active region in another direction
  • Multiple channel layers on the active region, spaced apart from each other in a third direction
  • Gate spacer layers on the side surfaces of the gate electrode layer
  • Source/drain regions on the active region, connected to the channel layers
  • An uppermost channel layer with separated channel portions below the gate spacer layers

Potential applications of this technology:

  • Integrated circuits
  • Microprocessors
  • Memory devices

Problems solved by this technology:

  • Improved performance and efficiency of semiconductor devices
  • Better control of current flow in the device

Benefits of this technology:

  • Higher speed and lower power consumption in electronic devices
  • Enhanced functionality and reliability of semiconductor devices


Original Abstract Submitted

A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode layer crossing the active region and extending in a second direction, a plurality of channel layers on the active region, spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and disposed sequentially from the active region, and surrounded by the gate electrode layer, gate spacer layers disposed on side surfaces of the gate electrode layer in the first direction, and source/drain regions disposed on the active region, on sides of the gate electrode layer, and connected to the plurality of channel layers. An uppermost channel layer among the plurality of channel layers includes channel portions separated from each other in the first direction and disposed below the gate spacer layers.