18195536. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18195536 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a first semiconductor chip, a chip stack on the first semiconductor chip, and a mold layer enclosing the chip stack on the first semiconductor chip. The chip stack consists of second semiconductor chips vertically stacked on the first semiconductor chip, a third semiconductor chip on top of the second semiconductor chips, and non-conductive layers filling the spaces between adjacent second semiconductor chips. The mold layer fills the spaces between the first semiconductor chip and the chip stack, as well as between the uppermost second semiconductor chip and the third semiconductor chip.
- The semiconductor package includes a chip stack with multiple semiconductor chips stacked vertically.
- Non-conductive layers are used to fill the spaces between the stacked semiconductor chips.
- A mold layer encloses the chip stack and the first semiconductor chip.
- The distances between the semiconductor chips and the mold layer are carefully controlled for optimal performance.
- Potential Applications
- This technology can be used in high-performance computing applications. - It can also be applied in advanced consumer electronics such as smartphones and tablets.
- Problems Solved
- The technology helps in increasing the packaging density of semiconductor chips. - It provides better thermal management for the stacked chips.
- Benefits
- Improved performance due to the compact design. - Enhanced reliability and durability of the semiconductor package. - Better thermal efficiency leading to reduced overheating issues.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip, a chip stack on the first semiconductor chip, and a mold layer enclosing the chip stack, on the first semiconductor chip. The chip stack includes second semiconductor chips vertically stacked on the first semiconductor chip, a third semiconductor chip on the second semiconductor chips, and non-conductive layers filling spaces between adjacent ones of the second semiconductor chips. The mold layer fills spaces between the first semiconductor chip and the chip stack, which are spaced apart from each other by a first distance, and between the uppermost one of the second semiconductor chips and the third semiconductor chip, which are spaced apart from each other by a second distance. The second semiconductor chips are spaced apart from each other by a third distance that is smaller than the first distance and the second distance.
