18192745. Repackaging IC Chip For Fault Identification simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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Repackaging IC Chip For Fault Identification

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chien-Yi Chen of Hsinchu City (TW)

Kao-Chih Liu of Changhua County (TW)

Chia Hong Lin of Hsinchu County (TW)

Yu-Ting Lin of Hsin-Chu City (TW)

Min-Feng Ku of Hsinchu City (TW)

Repackaging IC Chip For Fault Identification - A simplified explanation of the abstract

This abstract first appeared for US patent application 18192745 titled 'Repackaging IC Chip For Fault Identification

Simplified Explanation

The abstract of this patent application describes a testing tool that is configured to provide testing signals. These signals are routed to an integrated circuit (IC) die through a device-under-test (DUT) board. The IC die includes a substrate with multiple transistors, and it is sandwiched between the socket and the DUT board. The DUT board has a trench that extends partially into the IC die from one side. A signal detection tool is used to detect the electrical or optical signals generated by the IC die.

  • The testing tool is configured to provide testing signals.
  • The DUT board is configured to provide electrical routing.
  • The IC die is disposed between the socket and the DUT board.
  • The testing signals are routed to the IC die through the DUT board.
  • The IC die includes a substrate with multiple transistors.
  • A first structure with first metallization components is disposed over one side of the substrate.
  • A second structure with second metallization components is disposed over the opposite side of the substrate.
  • The DUT board has a trench that extends partially into the IC die from the second side.
  • A signal detection tool is used to detect the electrical or optical signals generated by the IC die.

Potential applications of this technology:

  • Testing and characterization of integrated circuits.
  • Quality control and reliability testing of IC dies.
  • Research and development of new IC designs.

Problems solved by this technology:

  • Efficient and accurate testing of IC dies.
  • Improved electrical routing and signal detection.
  • Enhanced reliability and performance of integrated circuits.

Benefits of this technology:

  • Faster and more reliable testing process.
  • Increased accuracy in detecting electrical or optical signals.
  • Improved quality control and reliability of integrated circuits.


Original Abstract Submitted

A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

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