18191212. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18191212 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract of the patent application describes a semiconductor package that includes a substrate with a redistribution layer, an interconnection chip, a via structure, an encapsulant, pillars, connection bumps, and chip structures. The first and second pillars have different shapes.
- The semiconductor package includes a substrate with a redistribution layer.
- An interconnection chip is located below the second surface of the substrate and is electrically connected to the redistribution layer.
- A via structure surrounds the interconnection chip and is electrically connected to the redistribution layer.
- An encapsulant is present between the second surface of the substrate, the interconnection chip, and the via structure.
- A first pillar extends through the encapsulant to electrically connect the redistribution layer and the interconnection circuit.
- A second pillar extends through the encapsulant to electrically connect the redistribution layer and the via structure.
- Connection bumps are located below the interconnection chip and the via structure.
- First and second chip structures are present on the first surface of the substrate and are electrically connected to the redistribution layer.
- The first and second pillars have different shapes.
Potential applications of this technology:
- Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
- Integrated circuits and microprocessors.
Problems solved by this technology:
- Provides electrical connections between different layers and components of a semiconductor package.
- Ensures reliable and efficient transmission of electrical signals.
- Helps in miniaturization and integration of electronic devices.
Benefits of this technology:
- Improved performance and functionality of electronic devices.
- Enhanced reliability and durability of semiconductor packages.
- Enables smaller and more compact electronic devices.
- Facilitates efficient heat dissipation in electronic devices.
Original Abstract Submitted
A semiconductor package includes a substrate including a first redistribution member including a first surface and a second surface, and including a first redistribution layer, an interconnection chip below the second surface and including an interconnection circuit electrically connected to the first redistribution layer, a via structure around the interconnection chip and electrically connected to the first redistribution layer, an encapsulant between the second surface and the interconnection chip and the via structure, a first pillar extending through the encapsulant to electrically connect the first redistribution layer and the interconnection circuit, a second pillar extending through the encapsulant to electrically connect the first redistribution layer and the via structure, and connection bumps below the interconnection chip and the via structure, and first and second chip structures on the first surface of the first redistribution member and electrically connected to the first redistribution layer. The first pillar and the second pillar have different shapes.
